High-speed and high-accuracy digital-to-analog (D/A) converters find many applications in signal processing. For wideband telecommunication systems, there is a strong demand on high-performance D/A converters. The requirements of distortion and intermodulation on this kind of D/A converters are very tough.
One of the major reasons causing distortion and intermodulation is due to transient current spikes. To illustrate the problem of transient current spikes, there is shown in FIG. 1a a 3-bit binary weighted D/A converter. There are three current sources with values Io, 2Io and 4Io. When the digital input b0 is 1, the current Io is switched to the output; when the digital input b1 is 1, the current 2Io is switched to the output; and when the digital input b2 is 1, the current 4Io is switched to the output.
Suppose there is a code transition from 011 to 100. Since it cannot be guaranteed that every bit switch operates simultaneously, there are different temporary codes as illustrated in FIG. 1b. Therefore, current spikes, or glitches appear at the output before the final values is reached. The glitches usually introduce distortion.
To reduce the glitch energy, another technique which is called segmentation can be used. A 3-bit segmented D/A converter is shown in FIG. 2a. Unlike binary weighted D/A converters, there are only unit current sources in segmented D/A converters. The 3-bit digital input data is first decoded into 7 outputs Q.sub.6.about.0 by a decoder 1. When the input data value is equal to J, there are only J outputs Q.sub.(J-1).about.O (J=7.about.1) having the output of 1. When the input data is equal to zero, all the outputs Q.sub.6.about.0 are zeros. When there is a code transition, say from 011 to 100 shown in FIG. 2b, there is only one bit switch Q.sub.3 changing the state. Therefore, glitch energy is minimized provided there is not intermediate output from the decoder 1 at a code transition. This can be guaranteed by using a latch at the decoder output.
Segmentation has its drawback. It needs more current sources and bit switches compared with binary weighting. In binary weighted CMOS D/A converters, unit current sources are usually employed to increase matching. This makes the current sources in binary weighted and segmented D/A converters identical. However, due to the fact that many more bit switches and wires are needed in segmented D/A converters, segmented D/A converters usually have smaller bandwidth and consume more chip area. To design high-performance D/A converters, combination of segmentation and binary weighting is a good choice.
Architectures combining segmentation and binary weighting have been used. An example is shown in FIG. 3, taken from J. M. Fournier and P. Senn, "A 130-Mhz 8-b CMOS video DAC for HDTV applications", IEEE J. Sold-State Circuits, July 1991, pp. 1073-1077. However, data have different delay for segmentation and binary weighting parts, limiting the speed. Also bit switches are not clocked by clock signals distributed to guarantee equal delay. Another serious problem is the implementation. The layout is organized into a matrix with each cell containing a current source, bit switch and local decoder.
The 6-bit MSB data in the cited reference are fed from above and right to some initial decoding circuit and then latched with latches 2. The 2-bit LSB data in the cited reference are directly latched without the delay function to equalize the delay in the data path. Therefore, very high frequency operation is not possible. In the matrix, each cell contains current source, bit switch and local decoder, which inflicts several problems as follows:
1) the matching of current sources is poor. Matching is a function of distance between current sources. The larger the distance is, the poorer the matching is. Due to the local decoders and bit switches, the distance between current sources are quite large; PA1 2) noise coupling is severe, because a lot of digital signal lines need to cross current sources. This problem gets severer with the increase of number of bits for segmentation; and PA1 3) glitch energy is still very high. Even though the changing of states at the output of the latches can be clocked, the control signals for the bit switches may differ significantly at the transition instance due to the different wire length from the latches to every bit switch. This creates glitch energy, introducing distortion and intermodulation. And the problem gets more severe with the increase of number of bits for segmentation.